发明名称 Adder, multiplier and integrated circuit
摘要 An adder includes a first XOR element for generating an XOR output of the first and the second data inputs, a first multiplexer for selecting one of the first carry input or the first data input while the XOR output is made a selection signal, a second multiplexer for selecting one of the second carry input or the second data input, a third multiplexer for selecting one of the first or the second carry inputs while the carry selection input is made a selection signal, and a second XOR element for generating an XOR output of an output of the third multiplexer and the XOR output, and is characterized in that an output of the first multiplexer is made a first carry output, an output of the second multiplexer is made a second carry output, and an output of the third multiplexer is made an addition value.
申请公布号 US2005076074(A1) 申请公布日期 2005.04.07
申请号 US20030648373 申请日期 2003.08.27
申请人 HORIE KIMITO 发明人 HORIE KIMITO
分类号 G06F7/507;G06F7/50;G06F7/503;G06F7/52;G06F7/523;G06F7/53;(IPC1-7):G06F7/50 主分类号 G06F7/507
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