A LOW LATENCY COMMA DETECTION CIRCUIT IN HIGH SPEED TRANSCEIVER

摘要

The present invention discloses a comma detection circuit is now integrated as part of the clock recovery circuit and a comma is detected before the data is serialized such that the latency is reduced. The comma detection circuit is also designed in analog CDR core to reduce the logic design uncertainty. Furthermore, by using advanced algorithms as disclosed in this invention, the number of transistors required to carry out the comma detection is greatly reduced. With reduced latency and fewer transistors now required for comma detection, more design flexibilities are provided for high transceiver designs such that bit order adjustments may be made with sufficient design flexibilities.