| 摘要 |
PROBLEM TO BE SOLVED: To provide layout equipment where a dummy cell is located near a correcting object circuit, and a chip size is not enlarged even if the dummy cell is added, and can create a netlist in proximy to a dummy cell stated hierarchy and a correcting object circuit stated hierarchy; and to provide its layout method. SOLUTION: In the layout design of a semiconductor device integrated circuit of a standard cell system, the layout equipment A of the semiconductor device integrated circuit includes a vacant area detecting means 10 which detects a vacant area after a macro cell and a mega cell, such as RAM, ROM, and CPU, are located, a determination means 12 which determines it is the most applicable that the dummy cells belonging to which logic function block are located in each of vacant areas, a dummy cell locating means 13 which locates as many as possible the dummy cells in the vacant areas, and a netlist construction means 19 which constructs the netlist containing the dummy cells, reflecting its result. The logic function block to which all the cells adjacent to the vacant area belong is detected, and the dummy cells which belong to the most logic function blocks are located in its vacant area. COPYRIGHT: (C)2005,JPO&NCIPI
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