| 摘要 |
A semiconductor testing apparatus capable of reducing time required for testing or repairing a plurality of semiconductor devices. The semiconductor testing apparatus performs test for a plurality of DUT in parallel and performs repair for the plurality of DUT in parallel. For this, the apparatus includes an ALPG, a PDS, an AFM, a driver pin processor, an IO pin processor, a driver channel, and an IO channel. The IO pin processor has a plurality of sub-FC units. When test is performed simultaneously for a plurality of DUT, an individual pattern waveform is generated corresponding to individual information.
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