| 摘要 |
PROBLEM TO BE SOLVED: To provide a multiport semiconductor memory which hardly gives rise to erroneous reading out due to coupling noise and is fast in operation speed. SOLUTION: In writing data from bit line pairs BLA, /BLA for an A port to memory cells 110-1 to 110-n, nMOS trsnsistors 161 and 162 turn on. The potential on a high level side of the bit line pairs BLA, /BLA coincides nearly with a power source potential VDD and therefore only the potential on a low level side is pulled up. Accordingly, the potential difference when either of the adjacent bit lines (BLA, and BLB or/BLA, /BLB) is a high level and the other turns to a low level is made smaller by the pull up and the generation time of the coupling noise is thereby made shorter. While the coupling noise is generated, the reading out of the data is not possible but the generation time thereof is made shorter and therefore the substantial operation speed is faster. COPYRIGHT: (C)2005,JPO&NCIPI
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