| 摘要 |
An efficient memory controller (12). The controller (12) includes a first mechanism (18, 28) for associating one or more input command sequences with one or more corresponding values. A second mechanism (20, 32) selectively sequences one of the one or more command sequences to a memory (16) in response to a signal. A third mechanism (30) compares each of the one or more values to a state of the second mechanism (20, 32) and provides the signal in response thereto. In a specific embodiment, the one or more corresponding values are execution time code values, and the second mechanism (20, 32) includes a sequencer state machine (32) that provides the state of the second mechanism (20, 32) as a sequencer time code. In the specific embodiment, a compare module (30) that compares the sequencer time code to a time code associated with a next available command sequence and execution time code pair and provides the signal in response thereto. |
