THREE DIMENSIONAL CMOS INTEGRATED CIRCUITS HAVING DEVICE LAYERS BUILT ON DIFFRENT CRYSTAL ORIENTED WAFERS

摘要

A three dimensional CMOS(Complementary Metal Oxide Semiconductor) IC(Integrated Circuit) is provided to obtain optimum performance from an NFET(N channel Field Effect Transistor) and a PFET by forming the PFET on a first semiconductor layer with a first crystal orientation and the NFET on a second semiconductor layer with a second crystal orientation. A first interconnection structure having a first SOI(Silicon On Insulator) substrate with a first surface orientation and a first semiconductor device on the first SOI substrate is provided. A handling wafer(80) is attached on the first interconnection structure. A second interconnection structure(50) having a second SOI substrate with a second surface orientation and a second device on the second SOI substrate is provided. The first and second interconnection structures are bonded to each other. The handling wafer is removed therefrom. The first and second semiconductor devices are a PFET and NFET, respectively.