发明名称 COLUMN SELECTION LINE CONTROLLING METHOD AND COLUMN SELECTION LINE CONTROLLING CIRCUIT
摘要 A method and a circuit for controlling a column select signal are provided to reduce test time by selecting a column control method according to an operation mode. A column select signal control circuit(500) is comprised of a first controller(510), a second controller(520), and a column select signal generator(530). The first controller inverts a first clock signal(PCSLEB) to output the inverted signal as a first control signal(CTRLS1). The second controller outputs a test operation signal(SDR) as a second control signal(CTRLS2) in a test operation mode. In a normal operation mode, the second controller inverts a second clock signal(PCSLDB) to output the inverted signal as the second control signal. In the test operation mode, the column select signal generator receives the first and second control signals and outputs a column select signal(CSL) activated in proportion to an activation time of the first control signal. In the normal operation mode, the column select signal generator is activated in response to the activation of the first control signal and outputs a non-activated the column select signal in response to the activation of the second control signal.
申请公布号 KR20050031679(A) 申请公布日期 2005.04.06
申请号 KR20030067913 申请日期 2003.09.30
申请人 SAMSUNG ELECTRONICS CO., LTD. 发明人 CHAE, MOO SUNG;CHOI, HYUNG CHAN
分类号 G11C11/40;G11C8/00;G11C11/408;G11C29/46;(IPC1-7):G11C11/40 主分类号 G11C11/40
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