发明名称 Exception types within a secure processing system
摘要 An apparatus for processing data includes a processor operable in a plurality modes including at least one secure mode being a mode in a secure domain and at least one non-secure mode being a mode in a non-secure domain. When the processor is executing a program in a secure mode the program has access to secure data which is not accessible when the processor is operating in a non-secure mode. The processor is responsive to one or more exception conditions for triggering exception processing using an exception handler. The processor is operable to select the exception handler from among a plurality of possible exception handlers in dependence upon whether the processor is operating in the secure domain or the non-secure domain.
申请公布号 GB0504192(D0) 申请公布日期 2005.04.06
申请号 GB20050004192 申请日期 2003.10.27
申请人 ARM LIMITED 发明人
分类号 G06F9/40;G06F9/46;G06F9/48;G06F11/00;G06F12/14;G06F21/74;H04L9/00 主分类号 G06F9/40
代理机构 代理人
主权项
地址