发明名称 DRAM cell structure with buried surrounding capacitor and process for manufacturing the same
摘要 A memory device that includes a semiconductor substrate, and an array of memory cells, each cell being electrically isolated from adjacent cells and including an island formed from the substrate, the island having a top portion and at least one sidewall portion, and being spaced apart from other islands by a bottom surface on the substrate, a capacitor formed contiguous with the sidewall portion, and a transistor formed on the top portion of the island, the transistor including a gate oxide layer formed on a surface of the top portion, a gate formed on the gate oxide layer, and a first and a second diffused regions formed in the top portion, the first diffused region being spaced apart from the second diffused region.
申请公布号 US6875653(B2) 申请公布日期 2005.04.05
申请号 US20020210031 申请日期 2002.08.02
申请人 PROMOS TECHNOLOGIES INC. 发明人 WANG TING-SHING
分类号 H01L21/8242;H01L27/02;H01L27/108;(IPC1-7):H01L21/824 主分类号 H01L21/8242
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