发明名称 |
Automatic generation of interconnect logic components |
摘要 |
A program tool automatically generating interconnect logic for a system-on-a-chip is based on a library of operational cores and on a architecture which requires all data exchange between cores to proceed via shared memory, which may be 'off-chip'. The architecture includes a data aggregation technique for access to memory with successive levels of arbitration.
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申请公布号 |
US6877145(B2) |
申请公布日期 |
2005.04.05 |
申请号 |
US20010919806 |
申请日期 |
2001.08.02 |
申请人 |
3COM CORPORATION |
发明人 |
BOYLAN SEAN;COBURN DEREK;CREEDON TADHG;DE PAOR DENISE;GAVIN VINCENT;HYLAND KEVIN J;HUGHES SUZANNE M;JENNINGS KEVIN;LARDNER MIKE;WALSH BRENDAN |
分类号 |
G06F17/50;(IPC1-7):G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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