发明名称 |
Mechanism for processing speclative LL and SC instructions in a pipelined processor |
摘要 |
A processor includes a first circuit and a second circuit. The first circuit is configured to provide a first indication of whether or not at least one reservation is valid in the processor. A reservation is established responsive to processing a load-linked instruction, which is a load instruction that is architecturally defined to establish the reservation. A valid reservation is indicative that one or more bytes indicated by the target address of the load-linked instruction have not been updated since the reservation was established. The second circuit is coupled to receive the first indication. Responsive to the first indication indicating no valid reservation, the first circuit is configured to select a speculative load-linked instruction for issued. The second circuit is configured not to select the speculative load-linked instruction for issue responsive to the first indication indicating the at least one valid reservation. A method is also contemplated.
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申请公布号 |
US6877085(B2) |
申请公布日期 |
2005.04.05 |
申请号 |
US20020068286 |
申请日期 |
2002.02.06 |
申请人 |
BROADCOM CORPORATION |
发明人 |
YEH TSE-YU;CHANG PO-YUNG;PEARCE MARK H.;CHEN ZONGJIAN |
分类号 |
G06F9/312;G06F9/38;(IPC1-7):G06F9/312 |
主分类号 |
G06F9/312 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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