发明名称 |
Static random access memory having leakage reduction circuit |
摘要 |
A static random access memory (SRAM) is provided that includes a logic circuit coupled to a column select signal line and a leakage reduction circuit coupled to the logic circuit and a bit line pair of a column. The logic circuit may control the leakage reduction circuit so as to reduce leakage through a column select device that is not selected.
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申请公布号 |
US6876571(B1) |
申请公布日期 |
2005.04.05 |
申请号 |
US20030738220 |
申请日期 |
2003.12.18 |
申请人 |
INTEL CORPORATION |
发明人 |
KHELLAH MUHAMMAD M.;SOMASEKHAR DINESH;YE YIBIN;DE VIVEK K. |
分类号 |
G11C11/00;G11C11/412;(IPC1-7):G11C11/00 |
主分类号 |
G11C11/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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