| 摘要 |
PROBLEM TO BE SOLVED: To provide a computer system and its signal generating circuit by which the timing of a chip select signal and a read/write signal can be rewritten and reset individually from the outside, without changing the basic design of the system even when the hardware configuration has been changed. SOLUTION: A chip select signal generator 61 and/or an IO read signal generator 62 (IO write signal generating part 63) is provided with a counter 60 which decides the start and finish time points of periods while the chip select signal (/IO_CS) and/or an IO write signal (/IO_WR), and an IO read signal (/IO_RD) are significant in correspondence with each of a plurality of chips, a register 61R01 or the like, a comparator 61C01 or the like, a flip-flop 61F0 or the like, and an OR gate 61G0 or the like. The start and finish time points of periods while the chip select signal (/IO_CS) and/or the IO write signal(/IO_WR), and the IO read signal (/IO_RD) are significant are set by a MPU. COPYRIGHT: (C)2005,JPO&NCIPI
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