发明名称 Method for fabricating wafer-level chip scale packages
摘要 A method for fabricating wafer-level chip scale packages is disclosed. A plurality of sacrificial photoresists with supporting surfaces in strip or bump configuration are formed on a surface of a wafer. Then, a negative photoresist layer is covered on the sacrificial photoresists. The negative photoresist layer is patterned in order to form a plurality of dielectric supporting bars on supporting surfaces of the sacrificial photoresists. Thereafter, a plurality of metal bars are formed on the dielectric supporting bars. Then the sacrificial photoresists are removed in order to form a plurality of pin terminals of the wafer-level chip scale packages for elastically surface-mounting to substrate or printed circuit board.
申请公布号 US2005070049(A1) 申请公布日期 2005.03.31
申请号 US20030671771 申请日期 2003.09.29
申请人 CHENG S. J.;LIU AN-HONG;WANG YEONG-HER;TSENG YUAN-PING;LEE Y. J. 发明人 CHENG S. J.;LIU AN-HONG;WANG YEONG-HER;TSENG YUAN-PING;LEE Y. J.
分类号 H01L21/44;H01L21/60;(IPC1-7):H01L21/44 主分类号 H01L21/44
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