发明名称 Algorithms tunning for dynamic lot dispatching in wafer and chip probing
摘要 A method and system for flexible, comprehensive, on-line, real-time dynamic lot dispatching in a semiconductor test foundry based on a two-phased, event-driven dispatching system structure. An adjustable priority formula and tuned algorithms integrated with PROMIS' constraint function give a nearly optimum dispatching list on any tester at any time with reduced mistake operations. Exception rules take care of special events to improve daily dispatching manual effort. This invention can automatically dispatch engineering lots according to engineering lots' capacity of Testing, solve conflict between wafer and package lots, efficiently reduce tester setup times, replace daily manual-dispatching sheet and keep a high CLIP rate while fully following MPS.
申请公布号 US2005071031(A1) 申请公布日期 2005.03.31
申请号 US20030672403 申请日期 2003.09.26
申请人 TAIWAN SEMICONDUCTOR MANUFACTURING CO. 发明人 LIN TA-CHIN;HUANG YI-FENG;LAI FU-KANG;HSIAO JEN-CHIH
分类号 G05B19/418;G06F19/00;(IPC1-7):G06F19/00 主分类号 G05B19/418
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