发明名称 DEVICE AND METHOD FOR CONTROLLING CACHE MEMORY
摘要 <P>PROBLEM TO BE SOLVED: To increase process efficiency by reducing power consumption of a cache memory. <P>SOLUTION: When data to be read is being read from a processor, a cache memory control device 1 detects whether or not the data expected to be read subsequently is cached. When the data expected to be read subsequently is stored in the cache, it is stored in a look-ahead cache part 20; when it is not stored in the cache, it is read from an external memory and stored in the look-ahead cache part 20. Thereafter, when the address of the data actually read from the processor in a subsequent cycle matches the address of the data stored in the look-ahead cache part 20, the data is outputted from the look-ahead cache part 20 to the processor. <P>COPYRIGHT: (C)2005,JPO&NCIPI
申请公布号 JP2005084999(A) 申请公布日期 2005.03.31
申请号 JP20030316884 申请日期 2003.09.09
申请人 SEIKO EPSON CORP 发明人 TODOROKI MITSUNARI
分类号 G06F12/08 主分类号 G06F12/08
代理机构 代理人
主权项
地址