| 摘要 |
A monolithically integrated vertical DMOS transistor device comprises a semiconductor substrate (11), a gate including a gate semiconductor layer region (27) on top of a gate insulation layer region (25), a source (31), a drain including a buried drain region (13) and a drain contact (21), and a channel region (29) arranged beneath the gate region. The drain comprises a lightly doped, preferably retrograde doped, drain region (23) arranged between the gate and the buried drain region, and the source (31), the channel region (29) and the lightly doped drain region (23) are arranged in a doped well region (17), wherein the lightly doped drain region has a higher doping level than the well region to thereby enhance the high frequency properties of the vertical DMOS transistor device.
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