Continuous self-verify of configuration memory in programmable logic devices

摘要

A programmable logic device (PLD) such as an FPGA or CPLD is supplementally configured to verify the integrity of its configuration data during operation of the device. The programmable logic device includes a checksum calculation engine to calculate a checksum based upon the configuration data. A checksum comparator compares the calculated checksum to a previously-calculated checksum to verify the integrity of the configuration data.