| 摘要 |
PROBLEM TO BE SOLVED: To securely prevent error writing into a non-selective memory cell by providing a selective transistor having enough withstand voltage against write inhibit voltage applied to a non-selective memory cell unit upon electron injection into the charge storage layer of a memory cell. SOLUTION: The memory cell unit comprises a semiconductor substrate 13 including a source diffusion layer 11, a columnar semiconductor layer 12 including a drain diffusion layer 7 on the uppermost part, a memory cell line connected in series vertically via a first impurity diffusion layer 9, a first selective transistor where one end of the memory cell line and the drain diffusion layer 7 are connected via a second impurity diffusion layer 8, and a second selective transistor where the other end of the memory cell line and the source diffusion layer 11 are connected via a third impurity diffusion layer 10. A distance between the third impurity diffusion layer and the source diffusion layer is set longer than a distance between the adjacent impurity diffusion layers putting each memory cell therebetween. Consequently, the punch-through of the second selective transistor can be avoided when write inhibit voltage is applied between the source diffusion layer and the first impurity diffusion layer. COPYRIGHT: (C)2005,JPO&NCIPI
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