发明名称 METHOD AND DEVICE FOR PACKAGING CHIP
摘要 PROBLEM TO BE SOLVED: To provide a precise and reliable parallelism measurement method and a precise and reliable parallelism adjustment method by measuring the parallelism between a bonding head and a substrate retention stage in the same state as an actual bonding. SOLUTION: In the parallelism measurement method for measuring the parallelism between the bonding head for retaining a chip and the substrate retention stage for retaining a substrate, the parallelism is measured, based on output from a pressure detection element, while a chip for calibration in which the pressure detection element is buried is sandwiched between the substrate retention stage for retaining the substrate and the bonding head for retaining the chip, and the chip for calibration is at least being pressurized. COPYRIGHT: (C)2005,JPO&NCIPI
申请公布号 JP2005085914(A) 申请公布日期 2005.03.31
申请号 JP20030314869 申请日期 2003.09.08
申请人 TORAY ENG CO LTD 发明人 YAMAUCHI AKIRA;TERADA KATSUMI;HARAI TAKASHI
分类号 H01L21/60;(IPC1-7):H01L21/60 主分类号 H01L21/60
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