发明名称 |
Computer system, compiler apparatus, and operating system |
摘要 |
A complier apparatus for a computer system that is capable of improving the hit rate of a cache memory is comprised of a prefetch target extraction device, a thread activation process insertion device, and a thread process creation device, and creates threads for performing prefetch and prepurge. Prefetch and prepurge threads created by this compiler apparatus perform prefetch and prepurge in parallel with the operation of the main program, by taking into consideration program priorities and the usage ratio of the cache memory.
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申请公布号 |
US2005071572(A1) |
申请公布日期 |
2005.03.31 |
申请号 |
US20040885708 |
申请日期 |
2004.07.08 |
申请人 |
NAKASHIMA KIYOSHI;HEISHI TAKETO;MICHIMOTO SHOHEI |
发明人 |
NAKASHIMA KIYOSHI;HEISHI TAKETO;MICHIMOTO SHOHEI |
分类号 |
G06F9/45;G06F9/46;G06F12/08;G06F15/16;(IPC1-7):G06F12/00 |
主分类号 |
G06F9/45 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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