发明名称 |
SEMICONDUCTOR MEMORY DEVICE AND ELECTRIC DEVICE WITH THE SAME |
摘要 |
A semiconductor memory device and an electric device with the same are provided to suppress the increase of a memory chip area by reducing the area of a row decoder. A cell array(1) has an electrically erasable nonvolatile memory cell arranged at each cross part of a plurality of bit lines and word lines, and a plurality of memory cells forms a NAND cell unit, and a plurality of blocks constituted with a plurality of NAND cell units arranged in parallel with a word line are arranged in a bit line direction. Row decoders(2a,2b) select the block of the cell array. The row decoder has a transmission transistor array(21) where transistors to transmit a word line driving voltage are arranged. A first decoder part(22) is prepared in each transmission transistor array, and drives the transmission transistor array selectively by supplying a boosting voltage. And a second decoder part(23) selects the block.
|
申请公布号 |
KR20050030609(A) |
申请公布日期 |
2005.03.30 |
申请号 |
KR20040077160 |
申请日期 |
2004.09.24 |
申请人 |
KABUSHIKI KAISHA TOSHIBA |
发明人 |
FUTATSUYAMA, TAKUYA;ICHIGE, MASAYUKI;SHIROTA, RIICHIRO;SUGIMAE, KIKUKO |
分类号 |
G11C16/06;G11C5/02;G11C5/06;G11C8/10;G11C8/12;G11C16/00;G11C16/04;G11C16/08;H01L21/8247;H01L27/00;H01L27/10;H01L27/115;H01L29/788;H01L29/792;(IPC1-7):G11C5/02 |
主分类号 |
G11C16/06 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|