发明名称 Bypassing pixel clock generation and CRTC circuits in a graphics controller chip
摘要 In a video processor unit, a method of providing a video data stream at a clock rate that is independent of a pixel clock rate. Receiving native video data from a video source at a native clock rate, storing the video data in a memory unit, reading selected portions of the video data at a memory clock rate, rasterizing the selected video data, packetizing the rasterized video data, sending the packetized video data to a display unit by way of a link at a link rate, wherein the link rate is directly related to the memory clock rate.
申请公布号 EP1519349(A2) 申请公布日期 2005.03.30
申请号 EP20040255609 申请日期 2004.09.16
申请人 GENESIS MICROCHIP, INC. 发明人 KOBAYASHI, OSAMU
分类号 G09G3/36;G06F3/14;G09G3/20;G09G5/00;G09G5/06;G09G5/395;H04N5/00;H04N5/44;H04N5/66;H04N7/12;H04N7/173;H04N21/431 主分类号 G09G3/36
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