Content addressable memory cell having improved layout

摘要

A CAM cell comprises a pair of SRAM cells, each of which comprise a pair of cross coupled inverters for storing a data value and a pair of access devices for accessing a complementary pair of bit lines. The CAM cell ether comprises a pair of compare circuits, each for comparing said data value stored in one of said SRAM cells with a search data value provided on a corresponding search line. The CAM cell has an equivalent number of n-channel and p-channel devices. The CAM cell uses p-channel transistors as access transistors to the SRAM cells in order to improve the efficiency of the layout of the cell array. The implementation ensures a balanced number of p-channel and n-channel devices per cell while still providing excellent functional characteristics.