Fault coverage and simplified test pattern generation for integrated circuits

摘要

An integrated circuit with improved testability includes a test logic component that replaces a corresponding regular logic component and that generates a logic high or low whenever a test input is activated. Alternatively, it may generate either high or low depending on which of two test inputs is activated. A test program may be augmented with instructions to activate such test inputs. An integrated circuit design may be analyzed to select a node that is not covered by a test program and to identify which logic component generates an output on the node. Then the design may be altered to replace the identified logic component with a corresponding test logic component. Test coverage analysis may be based on determining whether the test program toggles the node, or determining whether a stuck at fault on the node propagates so as to be observed.