SIGNAL LINE LAYOUT METHOD OF SEMICONDUCTOR MEMORY DEVICE

摘要

A signal line layout method of a semiconductor memory device is provided to maximize layout efficiency by minimizing a line pitch and an installation area of the line pitch. Each of first and second blocks(21,22) includes a plurality of first port couples for inputting/outputting a plurality of signal couples. The first and second blocks are opposed to each other to the horizontal direction. A third block(23) includes a plurality of second port couples for inputting/outputting a plurality of signal couples. The third block is arranged perpendicularly to the first and second blocks. The first port couples of the first and second blocks are opposite arranged to each other. The second port couples of the third block are divided into two groups plural opposite ports and plural ports. A plurality of first signal lines connected to the plural opposite ports and the plural ports of the third block are arranged in parallel to the first and second blocks. A plurality of second signal lines for connecting the first port couples to the second port couples are arranged perpendicularly to the first signal lines.