发明名称 Redundant memory self-test
摘要 A built-in-self-test circuit selectively couples memory outputs to fault detection circuitry during a self-test, thereby reducing the size of fault detection circuitry and storage required to properly test and repair a memory with multi-dimensional redundancy. The circuit may store information concerning memory elements having the greatest number of faults and select these for replacement prior to addressing redundancy in another dimension. Redundancy may then be allocated in the other dimension to repair any remaining faults. When a memory element, such as a column, has a greater number of fails than the number of perpendicular redundant elements, the memory element may be identified for immediate replacement.
申请公布号 US2005066226(A1) 申请公布日期 2005.03.24
申请号 US20030668651 申请日期 2003.09.23
申请人 ADAMS R. DEAN;MACDONALD ERIC W. 发明人 ADAMS R. DEAN;MACDONALD ERIC W.
分类号 G06F11/00;G11C29/44;(IPC1-7):G06F11/00 主分类号 G06F11/00
代理机构 代理人
主权项
地址