| 摘要 |
PROBLEM TO BE SOLVED: To downsize the scale of a power source circuit by reducing power consumption in a selection period of a ferroelectric capacitor. SOLUTION: In this memory device, in which ferroelectric memory cells (10) are arranged between word lines (W1-m) and bit lines (B1-n), at the time of read-operation, the prescribed voltage being higher than a positive anti-potential and lower than polarization saturation voltage can be applied between a selected word line and a selected bit line. Since the voltage applied to the ferroelectric capacitor (10) arranged between the word lines (W1-m) and the bit lines (B1-n) is higher than the anti-potential in a selection period, it is sufficient for read-out of a bit logic state, but it is lower than the polarization saturation voltage, thereby reducing the current flowing through the bit lines (B1-n) than heretofore to reduce the power consumption in the selection period. COPYRIGHT: (C)2005,JPO&NCIPI
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