STRUCTURE AND METHOD OF MAKING STRAINED CHANNEL CMOS TRANSISTORS HAVING LATTICE-MISMATCHED EPITAXIAL EXTENSION AND SOURCE AND DRAIN REGIONS
摘要
A structure and method are provided in which an n-type field effect transistor (NFET) and a p-type field effect transistor (PFET) each have a channel region disposed in a single-crystal layer of a first semiconductor and a stress is applied at a first magnitude to a channel region of the PFET but not at that magnitude to the channel region of the NFET. The stress is applied by a layer of a second semiconductor which is lattice-mismatched to the first semiconductor. The layer of second semiconductor is formed over the source and drain regions and extensions of the PFET at a first distance from the channel region of the PFET and is formed over the source and drain regions of the NFET at a second, greater distance from the channel region of the NFET, or not formed at all in the NFET.
申请公布号
WO2005027192(A2)
申请公布日期
2005.03.24
申请号
WO2004US28163
申请日期
2004.08.30
申请人
INTERNATIONAL BUSINESS MACHINES CORPORATION;DOKUMACI, OMER;CHEN, HUAJIE;CHIDAMBARRAO, DURESETI;YANG, HAINING, S.
发明人
DOKUMACI, OMER;CHEN, HUAJIE;CHIDAMBARRAO, DURESETI;YANG, HAINING, S.