<p>On implementation of the invention provides a stackable chip-scale package for improving memory density that may be mounted within a limited area or module. A novel staggered routing scheme enables the use of the same trace routing at every level of the stacked architecture for efficiently accessing individual memory devices in a chip-scale package stack. The use of a ball grid array chip-scale package architecture in combination with thermally compatible materials decreases the risk of thermal cracking while improving heat dissipation. Moreover, this architecture permits mounting support components, such as capacitors and resistors, on the chip-scale package.</p>
申请公布号
WO2005027225(A1)
申请公布日期
2005.03.24
申请号
WO2004US27653
申请日期
2004.08.25
申请人
SANMINA-SCI CORPORATION;ELLSBERRY, MARK;SCHMITZ, CHARLES, E.;CHEN, CHI, SHE;ALLISON, VICTOR
发明人
ELLSBERRY, MARK;SCHMITZ, CHARLES, E.;CHEN, CHI, SHE;ALLISON, VICTOR