发明名称 BUS BRIDGE CIRCUIT
摘要 PROBLEM TO BE SOLVED: To efficiently perform data access between a master device and a slave device without increasing a circuit scale. SOLUTION: When performing the data access to a plurality of slave devices 2 connected to a low-speed operation bus 7 from the master device 1 connected to a high-speed operation bus 6 through a bus bridge circuit 3, states of first and second state machines 4, 5 inside the bus bridge circuit 3 transit on the basis of access content from the master device 1 side and an internal state at that time point. Based on the states of the first and second state machines 4, 5, the bus bridge circuit 3 waits completion of the access on the slave device side operating at low speed, and performs wait control such that the access from the master device 1 side is completed. COPYRIGHT: (C)2005,JPO&NCIPI
申请公布号 JP2005078146(A) 申请公布日期 2005.03.24
申请号 JP20030304508 申请日期 2003.08.28
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 NISHIKAWA YOSHIKAZU
分类号 G06F13/36;G06F13/42;(IPC1-7):G06F13/36 主分类号 G06F13/36
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