发明名称 SCANNING TEST CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a scanning test circuit which secures setup time or hold time on scan shifting without exerting a delay influence on a circuit to be used for normal operations. SOLUTION: A clock signal 13 is supplied to flip-flops 4 to 6 to be used for the normal operations and the scanning test. Selector-equipped delay circuits 7 to 9 are provided to add a delay time, which is larger than that to be added when the normal operations are performed, to the clock signal 13 when the scanning test is performed. Both the normal operations and the scanning test are thereby operated with ample setup time and hold time secured. COPYRIGHT: (C)2005,JPO&NCIPI
申请公布号 JP2005077331(A) 申请公布日期 2005.03.24
申请号 JP20030310427 申请日期 2003.09.02
申请人 RENESAS TECHNOLOGY CORP;RENESAS LSI DESIGN CORP 发明人 DOBASHI TAKESHI
分类号 G01R31/28;G01R31/3185;H01L21/822;H01L27/04;(IPC1-7):G01R31/28 主分类号 G01R31/28
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