| 摘要 |
PROBLEM TO BE SOLVED: To provide a CMOS adder adapted to signed digit numbers which is manufactured in a normal inexpensive CMOS process and realizes a low power consumption. SOLUTION: The CMOS adder is provided with an addition part 1 which inputs two signals A and B represented by ternary signed digit numbers of "+1", "0", and "-1" and outputs an addition signal S1, and a carry part 2 which inputs two signals A and B and outputs a carry signal C1. The signal S1 is "-1" in the case that one of signals A and B is "+1" and the other is "0", and the signal S1 is "+1" in the case that one of signals A and B is "-1" and the other is "0", and the signal S1 is "0" in the other cases. The signal C1 is "+1" in the case that both of signals A and B are "+1" together or one of them is "+1" and the other is "0", and the signal S1 is "-1" in the case that both of signals A and B are "-1" together or one of them is "-1" and the other is "0", and the signal S1 is "0" in the other cases. COPYRIGHT: (C)2005,JPO&NCIPI
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