发明名称 Row redundancy memory repair scheme with shift to eliminate timing penalty
摘要 A memory having built-in self repair with row shifting is provided. The rows in the memory are divided into smaller row groups and a bad row group is repaired with a redundant row group. Each row group receives a row select signal, which is fed into a shift circuit for the row group and a shift circuit for an adjacent row group. A shift circuit is provided for the redundant row group and the shift circuit for the redundant row group receives the row select signal for only the adjacent row group. If a bad row group is detected, then starting with the row group furthest from the redundant row group, the shift circuit for each row group before the bad row group is deactivated. The row group select signal and word line signal for the bad row group are disabled. The shift circuit for the bad row group and the shift circuit for each row group after the bad row group are activated. Therefore, the bad row group is disabled and the redundant row group fills the void.
申请公布号 US6870782(B2) 申请公布日期 2005.03.22
申请号 US20030414516 申请日期 2003.04.15
申请人 LSI LOGIC CORPORATION 发明人 WU SIFANG;AGRAWAL GHASI R.;LECLAIR KEVIN R.
分类号 G11C7/00;G11C29/00;(IPC1-7):G11C29/00 主分类号 G11C7/00
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