发明名称 Failure analysis system of semiconductor memory device
摘要 In failure analysis method of a semiconductor memory device, an absolute value of a position difference between two fail bits of a two-dimensional bit map is calculated while a histogram corresponding to the absolute value of the position difference is updated. The bit map indicates a map of fail bits and each fail bit corresponds to a fail memory cell. The above calculation is repeated to all combinations of two of the fail bits in the bit map. Then, an expectation function value is calculated for each of values from the histograms and the number of the fail bits. Finally, whether the fail bits has regularity or irregularity for each value is determined based on the calculated expectation function value for the value.
申请公布号 US6871168(B1) 申请公布日期 2005.03.22
申请号 US20000570863 申请日期 2000.05.12
申请人 NEC ELECTRONICS CORPORATION 发明人 TANAKA MIKIO;SUGIMOTO MASAAKI;HAMADA TAKEHIKO
分类号 G01R31/28;G06F17/50;G11C29/00;G11C29/56;H01L21/66;(IPC1-7):G06F17/50 主分类号 G01R31/28
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