| 摘要 |
The present invention relates to a data processing system comprising a processor (100), at least one data memory (132), at least one program memory (134) and a main bus (110), common to the data and program memories and connecting these memories to the processor, characterized in that at least one of the memories has a rapid-access mode and in that the device also comprises a distribution interface (120) between the main bus (110) and the memories in order to alternately put in communication, by means of the main bus, one from among the data memory and the program memory with the processor, in a so-called active-access mode, and to keep the other memory in a so-called passive-access mode allowing subsequent rapid access.
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