| 摘要 |
A read amplifier (1) amplifies the output signal from the storage capacitor and is connected to evaluation logic circuitry. A counter connected between the read amplifier and the evaluation circuitry, receives a clock signal and converts the pulse width of the signal amplified by the read amplifier to a corresponding count state. The evaluation logic circuitry uses the height of the count state to determine if the signal was read from a region of the storage medium of the ferroelectric storage capacitor (Cferro) that has high positive polarisation, high negative polarisation, or weak polarisation. The width of the region of weak polarisation may be adjustable. |
