SEMICONDUCTOR MEMORY DEVICE CAPABLE OF ACCURATE AND STABLE OPERATION

摘要

A semiconductor memory device capable of accurate and stale operation is provided to prevent operation error between synchronization circuits where clock signals are applied. An external clock generation circuit(40) generates an external clock signal by being synchronized to a clock signal. An external control signal generation circuit receives an external command by being synchronized to the external clock signal, and generates an external control signal in response to the external command. A memory circuit(60) includes a memory cell array, and a read write circuit performing data read and data write as to the memory cell array. An internal control signal generation circuit receives the external control signal by being synchronized to an internal clock signal, and generates an internal control signal controlling the memory circuit in response to the external control signal. A mode instruction signal generation part(35) generates a mode instruction signal which becomes a first logic state as the memory circuit starts an internal operation mode and becomes the second logic state as the internal operation mode ends. And an internal clock generation circuit(50) generates the internal clock signal in response to the mode instruction signal of the first logic state. The external clock generation circuit stops the generation of the external clock signal in response to the mode instruction signal of the first logic state, and generates the external clock signal on the basis of the mode instruction signal of a second logic state.