发明名称 |
Memory device having a power down exit register |
摘要 |
A memory device including an array of memory cells, and a register circuit to store a value representative of a period of time to elapse before the memory device is ready to receive a command when recovering from a power down mode is provided in an embodiment. The command specifies an access to the array of memory cells. A delay lock loop circuit synchronizes data transfers using an external clock signal. The delay lock loop circuit reacquires synchronization with the external clock signal during the period of time.
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申请公布号 |
US2005060487(A1) |
申请公布日期 |
2005.03.17 |
申请号 |
US20040944320 |
申请日期 |
2004.09.17 |
申请人 |
BARTH RICHARD M.;TSERN ELY K.;HAMPEL CRAIG E.;WARE FREDERICK A.;BYSTROM TODD W.;MAY BRADLEY A.;DAVIS PAUL G. |
发明人 |
BARTH RICHARD M.;TSERN ELY K.;HAMPEL CRAIG E.;WARE FREDERICK A.;BYSTROM TODD W.;MAY BRADLEY A.;DAVIS PAUL G. |
分类号 |
G06F12/00;G06F13/16;G06F13/42;G11C7/10;G11C7/20;G11C11/4072;G11C11/4074;G11C11/4076;(IPC1-7):G06F12/00 |
主分类号 |
G06F12/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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