发明名称 MEMORY CONTROL UNIT
摘要 <p><P>PROBLEM TO BE SOLVED: To solve problems in a conventional memory control unit that since adjustment of an input and output clock can be confirmed only after production of a substrate because the clock is adjusted mainly by the wiring length of the substrate, and it is difficult to increase the data transfer speed because of individual dispersions of the substrate and a semiconductor part. <P>SOLUTION: This control unit comprises a delay circuit 103 capable of inserting a plurality of delays to an input signal or output signal, a delay selection circuit 102 for setting the quantity of delay to be inserted, and an optimum delay determination means 101 for determining the optimum quantity of delay. Accordingly, optimum delays for input or output or for the both are inserted. <P>COPYRIGHT: (C)2005,JPO&NCIPI</p>
申请公布号 JP2005070930(A) 申请公布日期 2005.03.17
申请号 JP20030297133 申请日期 2003.08.21
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 ITO NAOYUKI
分类号 G06F12/00;G06F1/10;(IPC1-7):G06F12/00 主分类号 G06F12/00
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