发明名称 |
SYSTEM AND METHOD FOR REDUCING THE LOCK TIME OF A PHASE LOCKED LOOP CIRCUIT |
摘要 |
<p>In accordance with the teachings described herein, systems and methods are provided for reducing the lock time of a phase locked loop circuit. A phase comparator may be used to detect a phase error between an input reference signal and a feedback clock signal. A frequency synthesizer circuit may be used to control the frequency of an ouput clock signal as a function of the phase error between the input signal and the feedback clock signal. A feedback divider may be used to divide the frquency of the output clock signal to generate the feedback clock signal. A phase error monitor may be used to detect when the phase error between the input signal and the feedback clock signal reaches a peak value, and in response to detecting the peak value, initialize the feedback divider to reduce the phase error between the input signal and the feedback clock signal.</p> |
申请公布号 |
WO2005025071(A1) |
申请公布日期 |
2005.03.17 |
申请号 |
WO2004CA01649 |
申请日期 |
2004.09.09 |
申请人 |
GENNUM CORPORATION;CORDOS, IOAN;CALBAZA, DORIN, E. |
发明人 |
CORDOS, IOAN;CALBAZA, DORIN, E. |
分类号 |
H03L7/00;H03L7/087;H03L7/089;H03L7/18;H03L7/199;(IPC1-7):H03L7/18 |
主分类号 |
H03L7/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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