SEMICONDUCTOR MEMORY WITH REDUCED PARASITIC CAPACITANCE AND MANUFACTURING METHOD THEREFOR

摘要

PROBLEM TO BE SOLVED: To provide a semiconductor memory device having reduced parasitic capacitance, and to provide its manufacturing method.

SOLUTION: The semiconductor memory includes a wordline formed on a predetermined part of a semiconductor substrate. A first spacer is formed on one sidewall of the wordline and a second spacer is formed on the other side wall. The source and drain regions are formed in both sides of the wordline on the semiconductor substrate and electrode interconnection lines are formed to make in contact with respective source and drain regions. One of these interconnection lines is an external signal line which is in contact with the source or drain region adjacent to the first spacer. The first spacer has relatively lower dielectric constant than the second spacer and these two spacers are preferably symmetrical.

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