| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a chip package adapted for reducing a process time to enable a reduction in cost and improvement in yield ratio, and also to provide the method of manufacturing the chip stack package. <P>SOLUTION: The chip stack package is provided with: a substrate having a first surface provided with a plurality of substrate terminals and a second surface provided with a plurality of connecting terminals electrically to connect with said substrate terminals; a first chip provided with an active surface in which a back surface and chip outer peripheries are formed, predetermined parts of a scribe lane formed in the extended localities outward from said chip outer peripheries of said active surface, and a plurality of first connecting vias formed penetrating the predetermined parts of a scribe lane, each having upper and lower surfaces; a second chip provided with an active surface in which a back surface and chip outer peripheries are formed, predetermined parts of a scribe lane formed in the extended localities outward from said chip outer peripheries of said active surface, and a plurality of second connecting vias formed penetrating said predetermined parts of the scribe lane, each having upper and lower surfaces. <P>COPYRIGHT: (C)2005,JPO&NCIPI |
