发明名称 Built-in jitter measurement circuit for voltage controlled oscillator and phase locked loop
摘要 A built-in jitter measurement circuit for a VCO (voltage-controlled oscillator) and a PLL (phase-locked loop) is disclosed. The circuit includes a divider for dividing frequency of a signal, a time to digital converter (TDC) for converting the period of the divided signal into digital values, a variance calculator for calculating variance of the period of the divided signal, a mean calculator for calculating mean value of the period of the divided signal, a encoder and counter for encoding and calculating the period of the divided signal, and a state controller as a controller for all other components. The circuit disclosed utilizes output clock of an opened-loop circuit to be measured and a divider for increasing jitter of the original signal. By measuring the bandwidth of a closed-loop circuit, accordingly, jitter of output clock of an opened-loop or an closed-loop circuit is measured by correlating the measured bandwidth and the jitter values from extrapolation.
申请公布号 US2005057312(A1) 申请公布日期 2005.03.17
申请号 US20040749560 申请日期 2004.01.02
申请人 INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE 发明人 CHANG YEONG-JAR;LIN SHEN-TIEN;WU WEN-CHING;LUO KUN-LUN
分类号 G01R29/26;H03L7/06;(IPC1-7):H03L7/00 主分类号 G01R29/26
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