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发明名称
增加积体电路构装密度之制造方法
摘要
本发明系揭露一种增加积体电路构装密度之制造方法,其系于一半导体底材上提供一闸极结构;形成一氧化薄层紧邻于闸极结构的侧面;并共形沉积一间隙壁材料于氧化薄层上;再形成一氧化物于间隙壁材料上,此氧化物具有一形状以覆盖间隙壁材料的一L形部分;接着移除氧化物以暴露出间隙壁材料的L形部分。此种具有L形间隙壁的闸极结构有利于空隙充填与避免接触至闸极的短路。
申请公布号
TW200511490
申请公布日期
2005.03.16
申请号
TW092125151
申请日期
2003.09.12
申请人
上海宏力半导体制造有限公司 GRACE SEMICONDUCTOR MANUFACTURING CORPORATION 中国
发明人
叶双凤;金平中
分类号
H01L21/76
主分类号
H01L21/76
代理机构
代理人
林火泉
主权项
地址
中国
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