| 摘要 |
<p>An error decoding circuit comprises a syndrome computing circuit (1a) for computing a syndrome on a receive data, an error detecting circuit (1b) for detecting an error based on the syndrome, an error pattern computing circuit (1c) for computing an error pattern based on the syndrome, and an inverting circuit (1d) for performing an error correction of a receive data based on the computed error pattern. Only when there is an error in the receive data, based on the detection result of the error detecting circuit (1b), a request signal for extension of a bus cycle is outputted to a bus master (2). On the other hand, if there is no error in the receive data, an inputted data is outputted to a data bus without correction. By so doing, the high speed operation of the data bus is executed. <IMAGE></p> |
