Direct memory access controller, direct memory access device, and request device

摘要

A direct memory access controller includes: one request signal input terminal for inputting a request signal while at least one of a plurality of request devices is outputting the request signal; one acknowledge signal output terminal for outputting an acknowledge signal to the plurality of request devices; and a control circuit. The control circuit outputs the acknowledge signal from the acknowledge signal output terminal and thereafter controls a data transfer based on the request signal from one of the plurality of request devices in response to a timing when the request signal inputted from the request signal input terminal changes in level.