发明名称 |
Method and apparatus for optimizing the timing of integrated circuits |
摘要 |
Integrated circuits are designed having optimal signal timing between and among cells. A set of identities are generated corresponding to logic operations and to library cells in technology basis. A resynthesis window is created for the identities having less than a predetermined depth of critical variables. Logic equations of the resynthesis window are transformed using the identities, and the resynthesized window area is optimized.
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申请公布号 |
US6868535(B1) |
申请公布日期 |
2005.03.15 |
申请号 |
US20010879841 |
申请日期 |
2001.06.12 |
申请人 |
LSI LOGIC CORPORATION |
发明人 |
PODKOLZIN ALEXANDER S.;KUDRYAVTSEV VALERY D. |
分类号 |
G06F17/50;(IPC1-7):G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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