| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a high speed interface power management system capable of efficiently reducing electric power consumption by a combination of a transfer rate and a communication protocol. <P>SOLUTION: The high speed interface power management system includes a clock control state machine 112 carrying out state transition on the basis of a state signal outputted from circuits 105-109 divided by the transfer rate and the communication protocol, and gate circuits 113-118 carrying out supply stoppage of a clock when a control signal outputted from the clock control state machine 112 is received. During high speed idling, clock supply is carried out to only an HSDLL 110 and an elasticity buffer 111. During high speed reception, clock supply is carried out to an HS data reception circuit 106 in addition to those in high speed idling. During high speed transmission, clock supply is carried out to only an HS data/device chirp transmission circuit 105. Clock supply stoppage is carried out in response to transmission/reception/idling during low speed transfer also to save power. <P>COPYRIGHT: (C)2005,JPO&NCIPI</p> |
